How does the cyclecomplete output port of the fiftyfivenm_crcblock WYSIWYG atom behave in MAX® 10 FPGAs?

Description

In MAX® 10 FPGAs, the cyclecomplete output port of the fiftyfivenm_crcblock WYSIWYG atom will assert high each time it completes a full chip error detection cycle.

Resolution

This information will be added to a future revision of the MAX® 10 FPGA Configuration User Guide.