How do I restore the original PLL counter settings (as defined in my Quartus II project) in my Altera device, after I have reconfigured the PLL with new counter settings?

Description

When using the ALTPLL megafunction, to restore the original PLL settings in your Altera® device, as defined in your Quartus® II project, you will need to either reconfigure the PLL again manually, with the original PLL settings, or reconfigure the FPGA itself (by asserting nCONFIG or power cycling the device). Asserting the areset port of the PLL will not restore the original counter settings after it has been reconfigured.

However, when using the Altera PLL megafunction, you can restore the original PLL settings by asserting the mgmt_reset signal on the Altera PLL_Reconfig megafunction, to reset all PLL counters to their initial values.

For both ALTPLL and Altera PLL megafunctions, asserting areset will lose any phase adjustments made (using Dynamic Phase Stepping for example) prior to the assertion of areset.