How do I provide the Advance Interface Bus (AIB) clock to the E-tile Hard IP for Ethernet Stratix® 10 FPGA IP using an IOPLL or a Native PHY in PLL Mode?

Description

Due to a restriction in the current release of the E-Tile Hard IP for Ethernet Stratix® 10 FPGA IP, external clock source cannot be used as an input to provide to the AIB clock.

Resolution

This capability is scheduled to be added to a future release of the Quartus® Prime Software.