How do I obtain the TSD offsets for designs targeting Intel® Stratix® 10 E and P tile devices when I use the IP Sense method to measure the junction temperature and the Intel® Stratix® 10 FPGA Early Power Estimator (EPE) to calculate the TSD offsets?

Description

The Intel® Stratix® 10 FPGA Early power Estimator version 19.4 and earlier, by default reports the Temperature Sensor Diode (TSD) offsets with respect to the temperature measured on the pinned out diode on the device. 

Resolution

If you are using the IP Sense to measure the temperature of your design, follow these steps to calculate the proper junction temperature:

1. Export the .csv from the Intel® Quartus® Prime Pro Edition Software  v19.4 or from the EPE 19.4 spreadsheet.
2. Open the .csv file in the 20.1 version of the Intel® Stratix® 10 FPGA Power and Thermal Calculator (PTC). The PTC reports TSD offsets for IP sense method of measuring the junction temperature. Use the reported TSD offsets in the PTC to calculate the junction temperature.
3. Save the file as a .ptc file for future manipulation.

If you are using the pinned out diode to make the temperature measurements, use the TSD offsets reported in v19.4 EPE.

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How do I obtain the TSD offsets for designs targeting Intel® Stratix® 10 E & P tile devices when I use the pinned out diode to measure the junction temperature temperature and the Intel® FPGA Power and Thermal Calculator (PTC) version 20.1 to calculate the TSD offsets?