How do I implement high-speed source synchronous interfaces in Arria 10?

Description

To implement high-speed source synchronous interfaces in Arria® 10 use the PHYLite IP.

The Altera® PHYLite for Parallel Interfaces IP core is primarily used for building custom memory interfaces. 

For example DDR2,  LPDDR2, LPDDR, TCAM, Flash, ONFI, and Mobile DDR. Each instance of the IP core can support an interface up to 18 individual data/strobe capture groups. Each group can contain up to 48 data I/Os and the strobe capture logic. PHYLite supports maximum interface clock frequency up to 1GHz.

Altera recommends using dynamic reconfiguration at 800 MHz or above. PHYLite supports most of common I/O standards, like SSTL-15, SSTL-15 Class I/II, 1.5-V HSTL Class I/II, 1.2 V POD, 1.2 V, 1,5 V, 1.8 V.

For more information of the PHYLite:

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_altera_phylite.pdf

Example project design of the PHYLite:

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an747.pdf

Altera strongly recommends implementing Source Synchronous I/O using Altera PHYLite for Parallel Interfaces IP core for interface frequency greater than 200MHz.