How do I implement a "One 18 x 19 Multiplication Summed with 36-Bit Input Mode" DSP function in an Intel® Arria® 10 device?

Description

To implement this (or other) advanced Intel® Arria® 10 FPGA digital signal processing (DSP) configuration, use the HDL templates available in the Quartus® II software.

Resolution

For a list of available templates, follow these steps:

1. Right-click in a VHDL or Verilog HDL file, and select Insert Template.
2. Select VHDL or Verilog HDL, then select Full Designs > Arithmetic > DSP Features > DSP Features for 20-nm device.