How do I generate a downstream hot reset from the Altera Hard IP for PCI Express Avalon-ST Root Port?

Description

The PCI Express® Specification Revision 3.0 describes a Hot Reset and how it is signaled on the link.

In the Altera® Root Port, setting bit[6] Secondary Bus Reset of the Bridge Control Register (0x03E), causes a Hot Reset. Refer to Section 7.5.3.6 of the PCIe Spec Revision 3.0.

This is a Type 1 Configuration Space register, which is accessed by issuing a Type 0 Configuration TLP.

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