Knowledge Base Article
How do I connect the F-Tile Reference and System PLL Clock IP out_coreclk_#i port to an IOPLL FPGA IP reference clock input in the Agilex 7™ FPGA devices?
Description
There is no dedicated connection from the F-Tile Reference and System PLL Clock IP out_coreclk_#i port to an IOPLL FPGA IP reference clock input in the Agilex™ 7 FPGA devices.
You may see an error message like this if you connect an F-Tile Reference and System PLL Clock IP out_coreclk_#i port directly to an IOPLL FPGA IP reference clock input.
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_PLDADAPT_RX(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure.Error(175020): The Fitter cannot place logic HSSI_PLDADAPT_RX in region (11, 65) to (11, 67), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info(14596): Information about the failing component(s):
Info(175028): The HSSI_PLDADAPT_RX name(s): FTL_auto_tiles|z1577b_x5_y0_n0|hdpldadapt_rx_chnl_21
...
Resolution
You can do the following to connect the F-Tile Reference and System PLL Clock IP out_coreclk_#i port to an IOPLL FPGA IP reference clock input.
- Divide the F-Tile Reference and System PLL Clock IP out_coreclk_#i signal by two in rtl.
- Connect the rtl divided out_coreclk_#i signal to a Clock Control FPGA IP buffer
- Connect the output of the Clock Control FPGA IP buffer to the IOPLL FPGA IP reference clock input.
The following example connects out_coreclk_2 of an F-Tile Reference and System PLL Clock IP to an IOPLL FPGA IP reference clock.
ref_sys_pll_clk_i0 : component ref_sys_pll_clk
port map (
out_systempll_synthlock_0 => out_systempll_synthlock_0,
out_systempll_clk_0 => out_systempll_clk_0,
out_refclk_fgt_2 => out_refclk_fgt_2,
in_refclk_fgt_2 => in_refclk_fgt_2,
out_coreclk_2 => out_coreclk_2);
process(out_coreclk_2)
begin
if rising_edge(out_coreclk_2) then
out_coreclk_2_2<= not out_coreclk_2_2;
end if ;
end process;
clkctrl_i0 : component clkctrl
port map (
inclk => out_coreclk_2_2,
clock_div1x => clkctrl_outclk);
iopll_i0 : component iopll
port map (
refclk => clkctrl_outclk,
locked => open,
rst => ninit_done(0),
outclk_0 => iopll_outclk_0);