How do I add the altreconfig block to my SOPC Builder and Qsys designs?

Description

When implementing PCIe® using SOPC Builder or Qsys, the ALTGX RECONFIG block is not included in the implementation and is not available from within SOPC Builder or Qsys.  You must include this block at the top-level design.  At a minimum, you will instantiate the SOPC Builder system that includes the PCIe block as well as an ALTGX RECONFIG block.  Also, for this solution it is assumed that a GPLL (general purpose PLL) for generating the reconfig_clk and fixedclk is also needed.  This GPLL can be eliminated if you can assure that these clocks are stable before the device comes out of the configuration state.

After generating the ALTGX RECONFIG block, you will need to enable the reconfig_reset input – details on this below.  This input allows holding the reconfiguration block in reset until the clocks, fixedclk and reconfig_clk, used for offset cancellation and receiver detect, are stable.  The necessary connection is to feed the locked signal from the GPLL, used to create the fixedclk and the reconfig_clk, through an inverter, into the reconfig_reset input.  It is also recommended that you synchronize this inverted PLL lock signal using the reconfig_clk, which is fed to the reconfiguration block clock input.

The GPLL  can be implemented via the MegaWizard™ Plug-in Manager, using the ALTPLL.  “fixedclk” must be 125MHz and the “reconfig_clk” must meet the requirements of your specific configuration, 37.5MHz – 50MHz for transmit and receive configuration of PCIE.  If you generate both fixedclk and reconfig_clk using the same PLL, nothing more is needed.  If multiple PLLs are needed, then the inverted locked signals must be OR'd prior to feeding the reconfig_reset signal.

Quartus® II software prior to 10.1 SP1:

To enable the reconfig_reset input you will need to run the following command at the command-line in the project directory where the ALTGX RECONFIG block is located.

qmegawiz -silent -wiz_override="offset_cancellation_reset" altgxb_reconfig_s4gx.v

Replacing <altgxb_reconfig_s4gx.v> with the MegaWizard generated altgxb reconfig block file name you provided in your design.

Quartus II software starting with 10.1 SP1:

To enable the reconfig_reset input on the ALTGX RECONFIG block, you will need to enable the “Channel and TX PLL select/reconfig” option on the “Reconfiguration settings” page, and enable the “Use ‘reconfig_reset’” option on the “Channel and TX PLL reconfiguration” page

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