How can the user logic RTL obtain the bus number and device number for the Intel® Arria® 10 and the Intel® Cyclone® 10 GX Avalon®-ST Interface for PCI Express*?

Description

The user logic needs to obtain the bus number and device number to generate TLPs correctly, but the bus number and device number are not output from the Intel® Arria® 10 and the Intel® Cyclone® 10 GX Avalon®-ST Interface for PCI Express*.

Resolution

To ascertain the bus number and device number the user logic RTL should read from the cfg_busdev register using the transaction layer configuration space signals.