How can I meet the Stratix V and Arria V GZ device ATX PLL calibration requirement that the transceiver reference clock must be present at the start of device configuration if I use the FPGA to program my clock synthesizer device?

Description

You can meet the Stratix® V and Arria® V GZ device ATX PLL calibration requirement that the transceiver reference clock must be present at the start of device configuration by programming a clock synthesizer device's One-Time Programmable (OTP) non-volatile memory with a default transceiver reference clock frequency.

Depending upon the clock-tree design, the reference clock would be available at the start of FPGA configuration and transceiver calibration requirements could be met. Reprogramming the clock synthesizer for a different frequency during FPGA user mode (perhaps via I2C) may still be possible depending upon the clock synthesizer device you are using.

The default transceiver reference clock frequency generated by the clock synthesizer device must match the default frequency expected by the FPGA device transceiver IP.

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• Why doesn't the tx_cal_busy signal assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria V GZ, and Stratix V GX/GT devices?
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