How accurate are the CDR Function Pins in the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA Pinout Files?

Description

Due to a problem in the pinout files and the Quartus® Prime Pro Edition Software version 25.1 and prior for the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA, the CDR function pin assignments in the bottom index sub-bank are incorrectly documented. Specifically:

• Pins with index 10/11, 22/23, 34/35, and 46/47 are mistakenly listed as supporting the CDR function.
• Conversely, pins with index 0/1, 12/13, 24/25, and 36/37, which do support the CDR function, are incorrectly marked as not supporting it.

Resolution

To work around this issue, users should update their board designs by reassigning the CDR function from the incorrect pin index to the correct ones as follows:

 

 

Designers are advised to validate pin assignments using the LVDS SERDES IP in Quartus® Prime Pro Edition Software rather than relying solely on the pinout files or Pin Planner.

 

This problem is scheduled to be fixed in the pinout files and in a future release of Quartus® Prime Pro Edition Software.