HMC Controller IP Core with Data Rate 12.5 Gbps Cannot Link with HMC Device when CDR Reference Clock Frequency is 166.67 MHz

Description

If you drive the reference clock for a Hybrid Memory Controller IP core variation with a data rate of 12.5 Gbps, at 166.67 MHz, the IP core cannot link up with the HMC device, due to an Arria 10 transceiver limitation. This issue impacts simulation and functionality in hardware.

This issue affects Hybrid Memory Cube Controller IP core variations with a data rate of 12.5 Gbps only.

Resolution

To avoid this issue, drive the reference clock of an HMC Controller IP core with a data rate of 12.5 Gbps at a frequency other than 166.67 MHz.