Fatal: SDF files require Altera primitive library

Description

Due to a problem in Modelsim-Altera software version 6.6c provided with the ACDS software version 10.1, you may see this error and errors such as those below during gate level timing simulation. This software bug only affects Verilog HDL timing simulations.

Loading instances from <design>_v.sdo
# ** Fatal: SDF files require Altera primitive library
#   Time: 0 ps  Iteration: 0  Instance: /<design>_tb  File: <drive>:/<path>/<design>_tb.v
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
#     Pausing macro execution
# MACRO ./<design>_run_msim_gate_verilog.do PAUSED at line 12

To work around this problem, simulate your gate-level netlist generated in the Quartus® II software version 10.1 with the ModelSim-Altera software version 6.5e provided with the ACDS software version 10.0 SP1.

This problem is fixed beginning with the ModelSim-Altera software version 6.6d provided with the Quartus II software version 10.1 SP1.