Failure: ARG is too large in CONV_INTEGER

Description

You may see this error while simulating the VHDL simulation model for double precision ALTERA_FP_MATRIX_MULT IP in the Mentor Modelsim or Aldec Riviera-PRO software.

Resolution

To work around this problem, use the Verilog HDL simulation model, or select Allow mixed-language simulation when generating the VHDL simulation model.