Excessive Warnings in the VHDL Design Example for Stratix V Hard IP for PCI Express IP Core

Description

Running the VHDL version of the Stratix V Hard IP for PCI Express IP design example in ModelSim results in excessive warnings of the following type:

**Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

These warning originate from the chaining DMA design example. They may fill up your transcript.

Resolution

To suppress these warnings, add the following command to your modelsim.ini file:

StdArithNoWarnings = 1