Example Design for Arria V with Hard Memory Interface Uses Wrong Clock

Description

This problem affects DDR2 and DDR3, QDR II, and RLDRAM II products.

The hard memory interface fabric in Arria V supports clock rates up to 267 MHz. The example design provided with the IP is clocked by pll_afi_clk, at 533 MHz. The example design should be clocked by pll_half_afi_clk instead.

Resolution

The workaround for this issue is to modify the example design to use pll_half_afi_clk instead of pll_afi_clk as the clock.

This issue will be fixed in a future version.