Errors in Post-Fit Simulation of EMIF Interfaces on Arria V and Cyclone V Devices

Description

This problem affects all external memory interfaces on Arria V and Cyclone V devices.

Designs containing an external memory interface may encounter simulation errors during post-fit simulation of either Verilog or VHDL, on Arria V or Cyclone V devices.

Resolution

The workaround for this issue is to not use post-fit simulation.

This issue will be fixed in a future version.