Error(18957): Signal ~GND is constrained to be routed locally to port CLK0 on destination XXXX|auto_fab_0|alt_sld_fab_0|*|sld_signaltap_inst|*|altera_syncram_impl1|ram_block2a0, but this signal must be routed through global network

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.2 and later, you might see this error when compiling a Partial Reconfiguration (PR) design with Signal Tap targeting an Agilex™ 7 F/I-series FPGA device.

Resolution

To workaround this problem, follow these steps:

1. Open the signal tap file.
2. Navigate to Signal Configuration pane. Under RAM type selection, 3 options will be available (Auto, M20K and MLAB).

        

3. Set the RAM type as MLAB as shown in the figure given below:

         

4. Save the signal tap file and run the full compilation.

Note: This restriction does not apply to Agilex™ 7 M-series production devices.