Error(13880): VHDL Binding Indication error at <VHDL File>: port in design entity does not have std_logic type that is specified for the same generic in the associated component.

Description

In the Quartus® Prime Pro Edition Software version 17.1 Update 1 and earlier, you may see this error message if you have a bitwidth of 1 which are written with std_logic_vertor(0 downto 0) in a VHDL file. Platfrom Designer will change it to std_logic automatically when it generates the synthesis files.

Resolution

To work around the problem, add the following property to the <custom _hw>.tcl file..

set_port_property <port_name> VHDL_TYPE std_logic_vector

If it’s a 1-bit signal, Platform Designer will assume it’s std_logic unless the above is specified