Error: (vsim-3033) ./../submodules/_modular_adc_0.v(26): Instantiation of '_modular_adc_0_control_internal' failed. The design unit was not found.

Description

Due to a problem with the Intel® MAX® 10 FPGA Modular ADC Intel® FPGA IP VHDL simulation setup, incorrect models are generated.

This error message is issued when VHDL simulation is started. It occurs due to an incorrect module name being used in automatically generated VHDL simulation models.  

Resolution

To work around this problem, use the Verilog HDL simulation model.

VHDL simulation is not supported for the Intel MAX 10 FPGA Modular ADC Intel FPGA IP.