Error: Verilog HDL error at altera_irq_clock_crosser.sv(21): module "altera_irq_clock_crosser" cannot be declared more than once File: <directory path>/altera_irq_clock_crosser.sv Line: 21

Description

Due to a problem in the Quartus® II software version 12.1, you may see this error during generation of Qsys systems that utilize IRQ Clock Crosser Logic.

Resolution

To workaround this problem follow the steps below:

1. Open the altera_irq_clock_crosser_hw.tcl file located in the Quartus II installation directory in a text editor:
              <Quartus II install directory>\ip\altera\merlin\altera_irq_clock_crosser
2. Remove the line:  "set_module_property SIMULATION_MODEL_IN_VERILOG true"
3. Add the line:  "add_file altera_irq_clock_crosser.sv {SYNTHESIS SIMULATION}"
4. Save the file and re-generate the Qsys system

This problem is fixed for the Quartus II software version 13.0 and later.