Error: Verilog generator FAILED. Refer to smc_fpga_dev.prj/main_e14d5d_2e367c.log for details. llvm-foreach

Description

Due to a problem in the Intel® OneAPI version 2022.3 in the DevCloud Environment, you may see this error in the backend profiler pass when you run a compilation with the attribute -Xprofile.

Resolution

To work around this problem in Devcloud, follow the steps below:

1. Turn off the -Xprofile flag (in your Makefile in the sentence: dpcpp -fintelfpga -Xsboard=intel_s10sx_pac:pac_s10 -Xshardware -Xsprofile -fsycl-link=image main.cpp -o smc_fpga_dev.a)
2. Save your Makefile
3. Compile again