Error Related to Incorrect Syntax of Type Conversion

Description

When you attempt to simulate a VHDL simulation model with VCS MX using NativeLink, compilation fails and reports an error message relating to incorrect syntax of type conversion.

This issue affects all VHDL designs targeting DDR, DDR2, or DDR3 with the high-performance controller II (HPC II) and ALTMEMPHY.

Compilation fails.

Resolution

Use Verilog rather than VHDL.

This issue will be fixed in a future version.