Error: Port (I or O) of I/O buffer * must be connected to a top-level pin.

Description

You may see this error in the Intel® Quartus® Prime Pro Edition Software when compiling a design that uses design partitions and a SystemVerilog interface.
The problem occurs when the following are true 

• the design partition module directly accesses internal members of a SystemVerilog interface 
• the SystemVerilog interface is instantiated outside of the design partition
• the SystemVerilog interface does not use a modport to define the directionality of that access across the partition boundary

    
Implementing a design partition on a module boundary that uses a SystemVerilog interface without specifying the direction of all ports within the interface through a modport is not supported.    

Resolution

To avoid this error, use the modport construct to explicitly define the direction of all signals within the interface across the partition boundary.