Error: PLL Output Counter parameter 'phase_shift' is set to an illegal value of <n>ns on node 'pll_ip:inst|pll_ip_0002:pll_ip_inst|altera_pll:altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER'.

Description

In Cyclone® V, the specifications below will give a fitter error. Also, the VCO frequency is more than the specified frequency from the datasheet.

Input 33.0 MHz

Output 1: 132 MHZ Phase shift 0.0 degree

Output 2: 158.4 MHz  Phase shift 5.0 degree

VCO frequency reported will be 1584.0 MHz.

Resolution

This is due to a bug in Intel® Quartus® version Cyclone® V PLL Megawizard. To work around this issue, create the PLL with the above specification in QSYS and add it to the design.