Error: PLL Output Counter parameter 'output_clock_frequency' is set to an illegal value of <clock frequency> on node gpll~PLL_OUTPUT_COUNTER'

Description

You may get this error in the Quartus® II software when the Device Speed Grade chosen in the Altera Phase-Locked Loop (Altera PLL) IP Core MegaCore® does not match the speed grade of your target Stratix® V, Arria® V or Cyclone® V device.

Resolution

Ensure the Device Speed Grade chosen in the Altera PLL IP Core MegaCore matches the speed grade of your target device.