Error nofile(37) in protected region

Description

You may experience the above error while simulating a VHDL-based DDR3 UniPHY memory controller design with ModelSim. When the DDR3 memory controller is generated in VHDL, all Verilog and SystemVerilog submodules are encrypted to allow simulation with a single-language simulator. If an error occurs in the encrypted fileset, a cryptic message like the one above will be generated.

Resolution

Make sure the DDR3 files are being compiled in the order specified in the msim_setup.tcl file located in the <variation_name>_sim directory. Any files compiled out-of-order may result in the above error.