Error: domain_0_default_slave: altera_error_response_slave does not support generation for VHDL Simulation

Description

Due to a problem with the Quartus® II software version 15.0 (windows only), Qsys systems that include the altera_error_response_slave IP, fails to generate VHDL simulation models and testbenches.

Resolution

To workaround this problem Verilog should be used for Simulation.

This problem will be fixed in future version of the QuartusII software.