Error (18496): Output is too close to PLL clock input pin

Description

You may see this error message when compiling a design targetting a MAX® 10 device with no pin assignment in the Quartus® Prime software version 16.1.

Resolution

To work around this issue, manually assign the location of the affected pin away from a PLL clock input pin in Assignment Editor.

This issue is fixed in Quartus Prime version 17.0.