Error (175006): There is no routing connectivity between the IOPLL and destination LVDS_CHANNEL

Description

You might see this error in the Intel® Quartus® Prime Pro Edition Software when using the LVDS SERDES Intel® FPGA IP with Intel® Stratix® 10 devices. This error occurs when the input clock signal of the IOPLL is being sourced through the FPGA core.

Resolution

To avoid this error, provide the input clock signal to the IOPLL through dedicated clock pins.