Error (16058): PLLs that use the x1 clock network and drive the same HSSI channel must be placed in the same transceiver bank

Description

Due to a problem with Intel® Quartus® Prime Standard Edition Software version 17.1, you may observe the above error if you are using Intel® FPGA SDI II IP with dynamic TX PLL switching enabled in Intel® Arria® V devices.

Resolution

There is no workaround for this problem. This problem is fixed starting with Intel® Quartus® Prime Standard Edition Software version 18.0.