Error (12012): Port direction mismatch for entity "altpcie_sv_hip_avmm_hwtcl:pcie_avgz_hip_avmm_0" at port "tlbfm_out[0]". Upper entity is expecting "Output" pin while lower entity is using "Input" pin.

Description

This error may be seen when trying to compile an Arria® V GZ or Stratix® V Hard IP for PCI Express® for the Avalon® Memory Mapped Qsys component in VHDL.

This problem is due to a Verilog HDL to VHDL conversion issue.

Resolution

Comment out the two offending tlbfm_out occurences from the top level wrapper in the file that is calling the altpcie_sv_hip_avmm_hwtcl component .

This problem is scheduled to be fixed in a future version of the Quartus® II software.