Error (10207): Verilog HDL error at <file>: can't resolve reference to object "<signal>"

Description

You may see this error if you reference a lower-level signal in Verilog HDL using hierarchical names according to the IEEE Standard Verilog Hardware Description Language section 12.4. The Quartus® II software does not support this syntax outside of simulation.

Resolution

To avoid this error, modify the output port list of the lower-level module to bring out the signal directly.