Knowledge Base Article
Error : Fail to verify file <filename>.svf
Description
You may see this error while programming an Intel® FPGA with an SVF file using the JTAG Chain Debugger in the Intel® Quartus® Prime Software.
This is known to occur if the SVF file is created with TCK set to 6 MHz and the Intel® FPGA Download Cable II (formerly known as the USB-Blaster II) is running at a default TCK value of 24 MHz.
If the SVF file is created with a TCK set to 25 MHz then this would work fine as long as the TCK of the Intel FPGA Download Cable II is not altered.
Resolution
If the SVF file is created with 6 MHz as TCK then the Intel® FPGA Download Cable II frequency should be brought down to 6 MHz to correlate with the SVF file setting.
To do this, open the Nios II Command Shell and type in the following command:
'jtagconfig --setparam 1 JtagClock 6M'