DSP Builder Generates Illegal VHDL

Description

DSP Builder generates illegal VHDL if you turn on Expose bus ports option on a FIR block that uses write-only coefficients.

The generated VHDL entity declaration for the FIR block has bus input ports but no bus output ports; the corresponding VHDL component declaration has both bus input and bus output ports.The Simulink block also (incorrectly) shows bus output ports.

Resolution

To work around this problem, use read/write coefficients on the FIR block.

This problem is fixed in DSP Builder v12.1.