Does Altera's PCIe core delete the TLP when BARs are defined as 32bit memory space and TLP for 64bit addressing is reached to PCIe core?

Description

Yes, if a 32 or 64-bit Memory transaction misses a BAR, it will get dropped inside the core and will not go on the user interface. The appropriate response will be transmitted automatically. The type of response depends on whether AER is enabled or disabled. With AER enabled, this response can be mapped differently.