Can the TxsByteEnable_i signals be used for both read and write transactions when using the Altera PCI Express Hard IP core in Avalon-MM mode?

Description

The Hard IP for PCI® Express with Avalon®-MM Interface user guides erroneously imply that the TxsByteEnable_i signals are only used as "Write byte enables".  These signals are actually used for both read and write requests. 

Resolution

The description in the table should read "Read and Write byte enables".  Also note that there are restrictions for Read byte enables, as described in the last paragraph of the "Avalon-MM-to-PCI Express Upstream Read Requests" section.  That paragraph should start:

For Avalon-MM read requests with a burst count greater than one, all byte enables must be asserted.  There are no restrictions on byte enables for Avalon-MM read requests with a burst count of one, other than the restrictions for continguous enables shown in the Avalon-MM TX Slave Interface Signals Table.

This detail will be included in a future release of the User Guides.