Can the start_of_burst and end_of_burst signals be asserted at the same time for the Serial Lite III FPGA IP on Arria® 10 and Stratix® 10 devices?

Description

Yes. The Serial Lite III FPGA IP supports a minimum one cycle burst length for the source data interface. You can assert the start_of_burst and end_of_burst signals on the same clock cycle for one cycle source data.

Resolution

N/A

Additional Information

N/A