Can the PLL reference clock input for Arria 10 external memory controllers be driven from another I/O PLL?

Description

No, PLL cascading is not supported for Arria® 10 EMIF IP. The balanced reference clock network required by EMIF IP and the PLL cascading clock network use the same underlying resources. Arria 10 EMIF PLL reference clock needs to be driven by a dedicated clock input pin.