Can the customer choose TI TUSB1210 chip as USB PHY?

Description

TSUB1210 is configured as Input clock mode.  The Cyclone V SoC Dev Kit is using USB3300 as Output clock mode.

Resolution

Arria V and Cyclone V USB 2.0 OTG controllers support the following clock modes:

• Output clock mode—the PHY drives the clock to the controller

• Input clock mode—the PHY is driven by an external clock source on the board or a clock input sourced from the FPGA fabric.

So input mode is supported. The customer must perform timing analysis to make sure their board design meets the spec, but it should work.