Can I set test_in ports of Arria II, Cyclone IV, and Stratix IV PCI Express IP core to all 0s?

Description

For normal operation you cannot set test_in ports to all 0s.

Please set the following test_in inputs to 1:
   bit[3] = FPGA mode.
   bit[5] = When set, prevents the LTSSM from entering compliance mode.
   bit[7] = Disables low power state negotiation.