Can I have multiple assignments to the same signal in a VHDL process statement?

Description

Yes, the Quartus^® II software supports multiple assignments to the same signal even though the last one assigned takes precedence.

However, if you are compiling in Quartus 2000.09 software or lower, and have not explicitly specified the range of your signals you results may not simulate properly.

Consider the following code:

 
----
signal a : std_logic_vector(7 downto 0);

process(iclock1,reset)
   if (reset='0') then
      a
----

When "reset" is '0', instead of getting "11100000" for the signal "a", Quartus software simulation shows the 2 most significant bits (MSBs) as flipped and displays the following: "00100011".

If you modify a to a (7 downto 0), the design will simulate correctly.

This problem is fixed in the Quartus II software version 1.0.