Can I constrain the asynchronous resets of the LVDS SERDES FPGA IP as false paths?

Description

When closing timing, the LVDS SERDES IP's asynchronous resets can be constrained as false paths, following the guidelines of the Quartus® Prime Pro Edition User Guide: Design Recommendations 2.3.1.2. Using Asynchronous Resets.

Resolution

When adding the necessary constraints to your SDC file, follow the guidelines in the Quartus® Prime Pro Edition User Guide: Design Recommendations.