Can a single fPLL output be used as a transceiver reference clock and also drive logic within the fabric on Stratix® V GX, Arria® V GX, and Arria® V GZ devices?

Description

No, a single fPLL output cannot be used as a transceiver reference clock source and also drive logic within the fabric on Stratix® V GX, Arria® V GX, and Arria® V GZ devices.

Resolution

To use the same fPLL to drive logic in the FPGA fabric, you can enable another fPLL output to drive your FPGA logic.