AXI channel deadlocks caused by unpipelined interconnects

Description

If you have a Qsys AXI interconnect that directly drives another Qsys AXI interconnect without any pipeline stages in between, a deadlock might occur between the write address channel and the write data channel. This can happen when the AXI bridges between separate interconnects are unpipelined.

Resolution

Insert a pipelined AXI bridge between the interconnect modules.