Are the sts_err_addr* and the sts_corr_dropped_addr registers supported by the Arria 10 EMIF (non-HPS) ECC-related MMR registers?

Description

Yes, the sts_err_addr* and the sts_corr_dropped_addr registers are supported.

At MMR register address 145, the sts_err_addr* is a 32-bit register and is the address of the most recent single-bit error (SBE) or double-bit error (DBE).
At MMR register address 146, the sts_corr_dropped_addr is a 32-bit register and is the address of the most recent correction command dropped.