Are the Partial Reconfiguration output pins on Stratix V, Arria V and Cyclone V devices configured as Open Drain by default, when these pins are enabled in my Quartus II project?

Description

In Quartus® II software versions 12.1 and earlier, if the Partial Reconfiguration (PR) pins are enabled for Stratix® V, Arria® V or Cyclone® V devices, the outputs will not be configured as Open Drain, and they will be powered by the VCCIO supply of the bank that they reside in.

Resolution

Open Drain functionality will be provided as an option for these pins in a future version of the Quartus II software.

When using Partial Reconfiguration are the PR_DONE, PR_READY, PR_ERROR, and PR_REQUEST pins powered by VCCPGM or VCCIO?

Updated 19 days ago

Version 2.0

Arria® V FPGAs and SoCs

Cyclone® V FPGAs and SoCs

Stratix® V FPGAs

troubleshooting

Knowledge Base Article

Are the Partial Reconfiguration output pins on Stratix V, Arria V and Cyclone V devices configured as Open Drain by default, when these pins are enabled in my Quartus II project?

Description

Resolution

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