Are the 64b/66b header bits compliant to the IEEE802.3ae standard when using Enhanced PCS with Basic mode in the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP and Transceiver Native PHY Intel® Arria® 10/Cyclone® 10 FPGA IP?

Description

No, the 64b/66b header bits are not compliant with the IEEE802.3ae standard when using Enhanced PCS with Basic mode in the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP and Transceiver Native PHY Intel® Arria® 10/Cyclone® 10 FPGA IP.

The IEEE802.3ae standard requires the header to be sent and received LSB first, with the control indication bit placed at bit[0].

Instead, the header bits are sent as MSB first when using in the L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP and Transceiver Native PHY Intel® Arria® 10/Cyclone® 10 FPGA IP in Enhanced PCS with Basic mode.

 

The L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP and Transceiver Native PHY Intel® Arria® 10/Cyclone® 10 FPGA IP are fully compliant with the IEEE802.3ae standard when configured in 10Gbase-R mode.

 

 

 

Resolution

To work around this problem in Enhanced PCS with Basic mode, you can implement the following:

• For the transmit direction: Delay the tx_ parallel_data by one clock cycle with respect to the tx_control data.
• For the receive direction: Delay the rx_control data by one clock cycle with respect to the rx_data.

 You can refer to the following code as an example.

This problem does not affect IEEE802.3ae compliance with Intel transceiver protocol IPs that don't use Enhanced PCS with Basic Mode.