Additive Latency Not Supported for HPS Hard Memory Controller in Arria V and Cyclone V SoC Devices

Description

This problem affects DDR2, DDR3, and LPDDR2 products.

Additive latency is not supported for interfaces targeting the HPS hard memory controller in Arria V or Cyclone V SoC HPS devices.

Resolution

There is no workaround for this issue.

This issue will be fixed in a future release.